Digital electronics and design with VHDL / (Record no. 2829)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 09185cam a2200313 a 4500 |
| 001 - CONTROL NUMBER | |
| control field | 14954463 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20181211112619.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 070806s2008 ne a b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER | |
| LC control number | 2007032518 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780123742704 (pbk. : alk. paper) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0123742706 (pbk. : alk. paper) |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)ocn164570635 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)164570635 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | DLC |
| Transcribing agency | DLC |
| Modifying agency | BAKER |
| -- | BTCTA |
| -- | YDXCP |
| -- | UKM |
| -- | OHX |
| -- | C#P |
| -- | DLC |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7885.7 |
| Item number | .P44 2008 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/2 |
| Edition number | 22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Pedroni, Volnei A. |
| 245 10 - TITLE STATEMENT | |
| Title | Digital electronics and design with VHDL / |
| Statement of responsibility, etc | Volnei A. Pedroni. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Amsterdam ; |
| Name of publisher, distributor, etc | Boston : |
| -- | Elsevier Morgan Kaufmann Publishers, |
| Date of publication, distribution, etc | c2008. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xxi, 693 p. : |
| Other physical details | ill. ; |
| Dimensions | 25 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc | Includes bibliographical references (p. 673-677) and index. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Contents <br/>Preface<br/>List of enumerated examples and exercises<br/>1 Introduction<br/>1.1 Historical notes<br/>1.2 Analog versus digital<br/>1.3 Bits, bytes, and words<br/>1.4 Digital circuits<br/>1.5 Combinational circuits versus sequential circuits <br/>1.6 Integrated circuits (ICs)<br/>1.7 Printed circuit board (PCB)<br/>1.8 Logic values versus physical values<br/>1.9 Non-programmable, programmable, and hardware-programmable<br/>1.10 Binary waveforms<br/>1.11 DC, AC, and transient responses<br/>1.12 Programmable logic devices (PLDs)<br/>1.13 Circuit synthesis and simulation with VHDL<br/>1.14 Circuit simulation with Spice<br/>1.15 Gate-level versus transistor-level analysis<br/>2 Binary representations<br/>2.1 Binary code<br/>2.2 Octal and hexadecimal codes<br/>2.3 Gray code<br/>2.4 BCD code<br/>2.5 Codes for negative numbers<br/>2.6 Floating-point representation<br/>2.7 ASCII code<br/>2.8 Unicode<br/>2.9 Exercises<br/>3 Binary arithmetic<br/>3.1 Unsigned addition<br/>3.2 Signed addition and subtraction<br/>3.3 Shift operations<br/>3.4 Unsigned multiplication<br/>3.5 Signed multiplication<br/>3.6 Unsigned division<br/>3.7 Signed division<br/>3.8 Floating-point addition and subtraction<br/>3.9 Floating-point multiplication<br/>3.10 Floating-point division<br/>3.11 Exercises<br/>4 Introduction to digital circuits<br/>4.1 Introduction to MOS transistors<br/>4.2 Inverter and CMOS logic<br/>4.3 AND and NAND gates<br/>4.4 OR and NOR gates<br/>4.5 XOR and XNOR gates<br/>4.6 Modulo-2 adder<br/>4.7 Buffer<br/>4.8 Tri-state buffer<br/>4.9 Open-drain buffer<br/>4.10 D-type flip-flop<br/>4.11 Shift register<br/>4.12 Counters<br/>4.13 Pseudo-random sequence generator<br/>4.14 Exercises<br/>5.1 Boolean algebra<br/>5.2 Truth tables<br/>5.3 Minterms and SOP equations<br/>5.4 Maxterms and POS equations<br/>5.5 Standard circuits for SOP and POS equations<br/>5.6 Karnaugh maps<br/>5.7 Large Karnaugh maps<br/>5.8 Other function-simplification techniques<br/>5.9 Propagation delay and glitches<br/>5.10 Exercises<br/>6 Line codes <br/>6.1 The use of line codes<br/>6.2 Parameters and types of line codes<br/>6.3 Unipolar codes<br/>6.4 Polar codes<br/>6.5 Bipolar codes<br/>6.6 Biphase/Manchester codes<br/>6.7 MLT codes<br/>6.8 mB/nB codes<br/>6.9 PAM codes<br/>6.10 Exercises<br/>7 Error-detecting/correcting codes <br/>7.1 Introduction<br/>7.2 Single-parity-check (SPC) codes<br/>7.3 Cyclic redundancy check (CRC) codes<br/>7.4 Hamming codes<br/>7.5 Reed Solomon codes<br/>7.6 Convolutional codes and Viterbi decoder<br/>7.7 Turbo codes<br/>7.8 Low-density parity-check (LDPC) codes<br/>7.9 Exercises<br/>8 Bipolar junction transistor (BJT)<br/>8.1 Semiconductors<br/>8.2 The bipolar junction transistor (BJT)<br/>8.3 I-V characteristics<br/>8.4 DC response<br/>8.5 Transient response<br/>8.6 AC response<br/>8.7 Modern BJTs<br/>8.8 Exercises<br/>9 MOS transistor<br/>9.1 Semiconductors <br/>9.2 The field-effect transistor (MOSFET)<br/>9.3 I-V characteristics<br/>9.4 DC response<br/>9.5 CMOS inverter<br/>9.6 Transient response<br/>9.7 AC response<br/>9.8 Modern MOSFETs<br/>9.9 Exercises<br/>10 Logic families and I/Os Logic architectures and I/Os<br/>10.1 BJT-based logic families<br/>10.2 Diode-transistor logic (DTL)<br/>10.3 Transistor-transistor logic (TTL)<br/>10.4 Emitter-coupled logic (ECL)<br/>10.5 MOS-based logic families<br/>10.6 CMOS logic<br/>10.7 Other static MOS architectures<br/>10.8 Dynamic MOS architectures<br/>10.9 Modern I/O standards<br/>10.10 Exercises<br/>11 Combinational logic circuits<br/>11.1 Combinational versus sequential logic<br/>11.2 Logical versus arithmetic circuits<br/>11.3 Fundamental logic gates <br/>11.4 Compound gates<br/>11.5 Encoders and decoders<br/>11.6 Multiplexer<br/>11.7 Parity detector<br/>11.8 Priority encoder<br/>11.9 Binary sorter<br/>11.10 Barrel shifters<br/>11.11 Non-overlapping clock generators<br/>11.12 Short-pulse generators<br/>11.13 Schmitt triggers<br/>11.14 Memories<br/>11.15 Exercises<br/>11.16 Exercises with VHDL<br/>11.17 Exercises with SPICE<br/>12 Combinational arithmetic circuits<br/>12.1 Arithmetic versus logical functions<br/>12.2 Basic adders<br/>12.3 Fast adders<br/>12.4 Bit-serial adder<br/>12.5 Signed adders/subtracters<br/>12.6 Incrementer, decrementer, and two¿s complementer<br/>12.7 Comparators<br/>12.8 ALU (arithmetic-logic unit)<br/>12.9 Multipliers<br/>12.10 Dividers<br/>12.11 Exercises<br/>12.12 Exercises with VHDL<br/>12.13 Exercises with SPICE<br/>13 Registers<br/>13.1 Sequential versus combinational logic<br/>13.2 SR latch (SRL)<br/>13.3 D latch (DL)<br/>13.4 D flip-flop (DFF)<br/>13.5 Master-slave DFFs<br/>13.6 Pulse-based DFFs<br/>13.7 Dual-edge DFFs<br/>13.8 Statistically low-power DFFs<br/>13.9 DFF control ports<br/>13.10 T flip-flop (TFF)<br/>13.11 Exercises<br/>13.12 Exercises with SPICE<br/>14 Sequential circuits<br/>14.1 Shift registers<br/>14.2 Synchronous counters<br/>14.3 Asynchronous counters<br/>14.4 Signal generators <br/>14.5 Frequency dividers<br/>14.6 PLL and prescalers<br/>14.7 Pseudo-random sequence generators<br/>14.8 Scramblers and descramblers<br/>14.9 Exercises<br/>14.10 Exercises with VHDL<br/>14.11 Exercises with SPICE<br/>15 Finite state machines<br/>15.1 FSM model<br/>15.2 Design of finite state machines<br/>15.3 System resolution and glitches<br/>15.4 Design of large FSMs<br/>15.5 Design of FSMs with complex combinational logic<br/>15.6 Design of symmetric-phase frequency dividers<br/>15.7 FSM encoding styles<br/>15.8 Exercises<br/>15.9 Exercises with VHDL<br/>16 Volatile memories<br/>16.1 Memory types<br/>16.2 SRAM (Static Random Access Memory)<br/>16.3 Dual and Quad Data Rate SRAMs (DDR and QDR)<br/>16.4 DRAM (Dynamic Random Access Memory)<br/>16.5 SDRAM (Synchronous DRAM)<br/>16.6 Dual Data Rate SDRAMs (DDR, DDR2, and DDR3)<br/>16.7 CAM (Content-Addressable Memory) for Cache Memories<br/>16.8 Exercises<br/>17 Non-volatile memories<br/>17.1 Memory types<br/>17.2 MP-ROM (Mask-Programmed ROM)<br/>17.3 OTP ROM (One-Time Programmable ROM or PROM)<br/>17.4 EPROM (Electrically Programmable ROM)<br/>17.5 EEPROM (Electrically Erasable-Programmable ROM)<br/>17.6 Flash memory<br/>17.7 Next generation memories: FRAM, MRAM, PRAM<br/>17.8 Exercises<br/>18 Programmable logic devices (PLDs)<br/>18.1 The concept of programmable logic devices<br/>18.2 SPLDs<br/>18.3 CPLDs<br/>18.4 FPGAs<br/>18.5 Exercises<br/>19 VHDL summary<br/>19.1 About VHDL <br/>19.2 Code structure<br/>19.3 Fundamental VHDL packages <br/>19.4 Pre-defined data types<br/>19.5 User-defined data types<br/>19.6 Operators<br/>19.7 Attributes<br/>19.8 Concurrent versus sequential code<br/>19.9 Concurrent code (WHEN, GENERATE)<br/>19.10 Sequential code (IF, CASE, LOOP, WAIT)<br/>19.11 Objects (CONSTANT, SIGNAL, VARIABLE)<br/>19.12 Packages<br/>19.13 Components<br/>19.14 Functions<br/>19.15 Procedures<br/>19.16 VHDL template for FSMs<br/>19.17 Exercises<br/>20 VHDL design of combinational logic circuits<br/>20.1: Generic address decoder<br/>20.2: BCD-to-SSD conversion function<br/>20.3: Generic multiplexer<br/>20.4: Generic priority encoder<br/>20.5: Design of ROM memory<br/>20.6 Design of Synchronous RAM Memories<br/>20.7 Exercises<br/> <br/>21 VHDL design of combinational arithmetic circuits<br/>21.1 Carry-ripple adder<br/>21.2 Carry-lookahead adder<br/>21.3 Signed and unsigned adders / subtracters<br/>21.4 Signed and unsigned multipliers / dividers <br/>21.5 ALU<br/>21.6 Exercises <br/>22 VHDL design of regular sequential circuits <br/>22.1 Shift register with load<br/>22.2 Switch debouncer<br/>22.3 Timer<br/>22.4 Fibonacci series generator<br/>22.5 Frequency meters<br/>22.6 Neural networks<br/>22.7 Exercises <br/>23 VHDL design of state machines<br/>23.1 String detector<br/>23.2 ¿Universal¿ signal generator<br/>23.3 Car alarm<br/>23.4 LCD driver<br/>23.5 Exercises <br/>24 Simulation with VHDL testbenches<br/>24.1 Synthesis versus simulation<br/>24.2 Stimulus generation<br/>24.3 Writing testbenches ¿ part 1<br/>24.4 Writing testbenches ¿ part 2<br/>24.5 Functional simulations<br/>24.6 Timing simulations<br/>24.7 Exercises<br/>25 Simulation with SPICE<br/>25.1 About SPICE<br/>25.2 Types of analysis<br/>25.3 Basic structure of SPICE code<br/>25.4 Declarations of electronic devices<br/>25.5 Declarations of independent DC sources<br/>25.6 Declarations of independent AC sources<br/>25.7 Declarations of dependent sources<br/>25.8 SPICE inputs and outputs<br/>25.9 DC response examples<br/>25.10 Transient response examples<br/>25.11 AC response example<br/>25.12 Subcircuits<br/>25.13 Exercises involving combinational logic circuits<br/>25.14 Exercises involving combinational arithmetic circuits<br/>25.15 Exercises involving registers<br/>25.16 Exercises involving sequential circuits<br/>Appendices<br/>A ModelSim Tutorial<br/>B PSpice Tutorial<br/>References <br/>Index |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | VHDL (Computer hardware description language) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Digital integrated circuits |
| General subdivision | Design and construction |
| -- | Data processing. |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) | |
| a | 7 |
| b | cbc |
| c | orignew |
| d | 1 |
| e | ecip |
| f | 20 |
| g | y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Item type | Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total Checkouts | Full call number | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Centeral Library | Centeral Library | Second Floor - Engineering & Architecture | 16.11.2016 | 621.392 P.V.D 2008 | 11552 | 16.11.2016 | 16.11.2016 | Books |