000			09127cam a2200409Ka 4500
999			_c2866 _d2866
001			700167288
003			OCoLC
005			20180421115108.0
006			m d
007			cr cn|||||||||
008			110203s2011 nyua ob 001 0 eng d
020			_a9781441975485 (electronic bk.)
020			_a1441975489 (electronic bk.)
035			_a(OCoLC)700167288 _z(OCoLC)695849409
037			_a978-1-4419-7547-8 _bSpringer _nhttp://www.springerlink.com
040			_aGW5XE _beng _cGW5XE _dOCLCQ _dQE2 _dMYPMP _dSNK
050		4	_aTK7874 _b.N38 2011
082	0	4	_a621.3815 _222
100	1		_aNavabi, Zainalabedin
245	1	0	_aDigital system test and testable design _busing HDL models and architectures / _cZainalabedin Navabi
250			_a1st ed.
260			_aNew York : _bSpringer, _cc2011
300			_a1 online resource (xxiii, 435 p.) : _bill
504			_aIncludes bibliographical references and index
505	0	0	_aNote continued: _g2.8.3. _tSimple Sequential Testbench -- _g2.8.4. _tLimiting Data Sets -- _g2.8.5. _tSynchronized Data and Response Handling -- _g2.8.6. _tRandom Time Intervals -- _g2.8.7. _tText IO -- _g2.8.8. _tSimulation Code Coverage -- _g2.9. _tPLI Basics -- _g2.9.1. _tAccess Routines -- _g2.9.2. _tSteps for HDL/PLI Implementation -- _g2.9.3. _tFault Injection in the HDL/PLI Environment -- _g2.10. _tSummary -- _tReferences -- _g3. _tFault and Defect Modeling -- _g3.1. _tFault Modeling -- _g3.1.1. _tFault Abstraction -- _g3.1.2. _tFunctional Faults -- _g3.1.3. _tStructural Faults -- _g3.2. _tStructural Gate Level Faults -- _g3.2.1. _tRecognizing Faults -- _g3.2.2. _tStuck-Open Faults -- _g3.2.3. _tStuck-at-0 Faults -- _g3.2.4. _tStuck-at-1 Faults -- _g3.2.5. _tBridging Faults -- _g3.2.6. _tState-Dependent Faults -- _g3.2.7. _tMultiple Faults -- _g3.2.8. _tSingle Stuck-at Structural Faults -- _g3.2.9. _tDetecting Single Stuck-at Faults -- _g3.3. _tIssues Related to Gate Level Faults -- _g3.3.1. _tDeteeting Bridging Faults -- _g3.3.2. _tUndetectable Faults -- _g3.3.3. _tRedundant Faults -- _g3.4. _tFault Collapsing -- _g3.4.1. _tIndistinguishable Faults -- _g3.4.2. _tEquivalent Single Stuck-al Faults -- _g3.4.3. _tGate-Oriented Fault Collapsing -- _g3.4.4. _tLine-Oriented Fault Collapsing -- _g3.4.5. _tProblem with Reconvergenl Fanouts -- _g3.4.6. _tDominance Fault Collapsing -- _g3.5. _tFault Collapsing in Verilog -- _g3.5.1. _tVerilog Testbench for Fault Collapsing -- _g3.5.2. _tPLI Implementation of Fault Collapsing -- _g3.6. _tSummary -- _tReferences -- _g4. _tFault Simulation Applications and Methods -- _g4.1. _tFault Simulation -- _g4.1.1. _tGate-Level Fault Simulation -- _g4.1.2. _tFault Simulation Requirements -- _g4.1.3. _tHDL Environment -- _g4.1.4. _tSequential Circuit Fault Simulation -- _g4.1.5. _tFault Dropping -- _g4.1.6. _tRelated Terminologies -- _g4.2. _tFault Simulation Applications -- _g4.2.1. _tFault Coverage -- _g4.2.2. _tFault Simulation in Test Generation --
505	0	0	_aNote continued: _g4.2.3. _tFault Dictionary Creation -- _g4.3. _tFault Simulation Technologies -- _g4.3.1. _tSerial Fault Simulation -- _g4.3.2. _tParallel Fault Simulation -- _g4.3.3. _tConcurrent Fault Simulation -- _g4.3.4. _tDeductive Fault Simulation -- _g4.3.5. _tComparison of Deductive Fault Simulation -- _g4.3.6. _tCritical Path Tracing Fault Simulation -- _g4.3.7. _tDifferential Fault Simulation -- _g4.4. _tSummary -- _tReferences -- _g5. _tTest Pattern Generation Methods and Algorithms -- _g5.1. _tTest Generation Basics -- _g5.1.1. _tBoolean Difference -- _g5.1.2. _tTest Generation Process -- _g5.1.3. _tFault and Tests -- _g5.1.4. _tTerminologies and Definitions -- _g5.2. _tControllability and Observability -- _g5.2.1. _tControllability -- _g5.2.2. _tObservability -- _g5.2.3. _tProbability-Based Controllability and Observability -- _g5.2.4. _tSCOAP Controllability and Observability -- _g5.2.5. _tDistances Based -- _g5.3. _tRandom Test Generation -- _g5.3.1. _tLimiting Number of Random Tests -- _g5.3.2. _tCombinational Circuit RTG -- _g5.3.3. _tSequential Circuit RTG -- _g5.4. _tSummary -- _tReferences -- _g6. _tDeterministic Test Generation Algorithms -- _g6.1. _tDeterministic Test Generation Methods -- _g6.1.1. _tTwo-Phase Test Generation -- _g6.1.2. _tFault-Oriented TG Basics -- _g6.1.3. _tD-Algorithm -- _g6.1.4. _tPODEM (Path-Oriented Test Generation) -- _g6.1.5. _tOther Deterministic Fault-Oriented TG Methods -- _g6.1.6. _tFault-Independent Test Generation -- _g6.2. _tSequential Circuit Test Generation -- _g6.3. _tTest Data Compaction -- _g6.3.1. _tForms of Test Compaction -- _g6.3.2. _tTest Compatibility -- _g6.3.3. _tStatic Compaction -- _g6.3.4. _tDynamic Compaction -- _g6.4. _tSummary -- _tReferences -- _g7. _tDesign for Test by Means of Scan -- _g7.1. _tMaking Circuits Testable -- _g7.1.1. _tTradeoffs -- _g7.1.2. _tTesting Sequential Circuits -- _g7.1.3. _tTestability of Combinational Circuits -- _g7.2. _tTestability Insertion -- _g7.2.1. _tImproving Observability --
505	0	0	_aNote continued: _g7.2.2. _tImproving Controllability -- _g7.2.3. _tSharing Observability Pins -- _g7.2.4. _tSharing Control Pins -- _g7.2.5. _tReducing Select Inputs -- _g7.2.6. _tSimultaneous Control and Observation -- _g7.3. _tFull Scan DFTTechnique -- _g7.3.1. _tFull Scan Insertion -- _g7.3.2. _tFlip-Flop Structures -- _g7.3.3. _tFull Scan Design and Test -- _g7.4. _tScan Architectures -- _g7.4.1. _tFull Scan Design -- _g7.4.2. _tShadow Register DFT -- _g7.4.3. _tPartial Scan Methods -- _g7.4.4. _tMultiple Scan Design -- _g7.4.5. _tOther Scan Designs -- _g7.5. _tRT Level Scan Design -- _g7.5.1. _tRTL Design Full Scan -- _g7.5.2. _tRTL Design Multiple Scan -- _g7.5.3. _tScan Designs for RTL -- _g7.6. _tSummary -- _tReferences -- _g8. _tStandard IEEE Test Access Methods -- _g8.1. _tBoundary Scan Basics -- _g8.2. _tBoundary Scan Architecture -- _g8.2.1. _tTest Access Port -- _g8.2.2. _tBoundary Scan Registers -- _g8.2.3. _tTAP Controller -- _g8.2.4. _tDecoder Unit -- _g8.2.5. _tSelect and Other Units -- _g8.3. _tBoundary Scan Test Instructions -- _g8.3.1. _tMandatory Instructions -- _g8.4. _tBoard Level Scan Chain Structure -- _g8.4.1. _tOne Serial Scan Chain -- _g8.4.2. _tMultiple-Scan Chain with One Control Test Port -- _g8.4.3. _tMultiple-Scan Chains with One TDI, TDO but Multiple TMS -- _g8.4.4. _tMultiple-Scan Chain, Multiple Access Port -- _g8.5. _tRT Level Boundary Scan -- _g8.5.1. _tInserting Boundary Scan Test Hardware for CUT -- _g8.5.2. _tTwo Module Test Case -- _g8.5.3. _tVirtual Boundary Scan Tester -- _g8.6. _tBoundary Scan Description Language -- _g8.7. _tSummary -- _tReferences -- _g9. _tLogic Built-in Self-test -- _g9.1. _tBIST Basics -- _g9.1.1. _tMemory-based BIST -- _g9.1.2. _tBIST Effectiveness -- _g9.1.3. _tBISTTypes -- _g9.1.4. _tDesigning a BIST -- _g9.2. _tTest Pattern Generation -- _g9.2.1. _tEngaging TPGs -- _g9.2.2. _tExhaustive Counters -- _g9.2.3. _tRing Counters -- _g9.2.4. _tTwisted Ring Counter -- _g9.2.5. _tLinear Feedback Shift Register --
505	0	0	_aNote continued: _g9.3. _tOutput Response Analysis -- _g9.3.1. _tEngaging ORAs -- _g9.3.2. _tOne's Counter -- _g9.3.3. _tTransition Counter -- _g9.3.4. _tParity Checking -- _g9.3.5. _tSerial LFSRs (SISR) -- _g9.3.6. _tParallel Signature Analysis -- _g9.4. _tBIST Architectures -- _g9.4.1. _tBTST-related Terminologies -- _g9.4.2. _tCentralized and Separate Board-level BIST Architecture (CSBL) -- _g9.4.3. _tBuilt-in Evaluation and Self-test (BEST) -- _g9.4.4. _tRandom Test Socket (RTS) -- _g9.4.5. _tLSSD On-chip Self Test -- _g9.4.6. _tSelf-testing Using MTSR and SRSG -- _g9.4.7. _tConcurrent BIST -- _g9.4.8. _tBILBO -- _g9.4.9. _tEnhancing Coverage -- _g9.5. _tRT Level BIST Design -- _g9.5.1. _tCUT Design, Simulation, and Synthesis -- _g9.5.2. _tRTS BIST Insertion -- _g9.5.3. _tConfiguring the RTS BIST -- _g9.5.4. _tIncorporating Configurations in BIST -- _g9.5.5. _tDesign of STUMPS -- _g9.5.6. _tRTS and STUMPS Results -- _g9.6. _tSummary -- _tReferences -- _g10. _tTest Compression -- _g10.1. _tTest Data Compression -- _g10.2. _tCompression Methods -- _g10.2.1. _tCode-based Schemes -- _g10.2.2. _tScan-based Schemes -- _g10.3. _tDecompression Methods -- _g10.3.1. _tDecompression Unit Architecture -- _g10.3.2. _tCyclical Scan Chain -- _g10.3.3. _tCode-based Decompression -- _g10.3.4. _tScan-based Decompression -- _g10.4. _tSummary -- _tReferences -- _g11. _tMemory Testing by Means of Memory BIST -- _g11.1. _tMemory Testing -- _g11.2. _tMemory Structure -- _g11.3. _tMemory Fault Model -- _g11.3.1. _tStuck-At Faults -- _g11.3.2. _tTransition Faults -- _g11.3.3. _tCoupling Faults -- _g11.3.4. _tBridging and State CFs -- _g11.4. _tFunctional Test Procedures -- _g11.4.1. _tMarch Test Algorithms -- _g11.4.2. _tMarch C-Algorithm -- _g11.4.3. _tMATS+Algorithm -- _g11.4.4. _tOther March Tests -- _g11.5. _tMBIST Methods -- _g11.5.1. _tSimple March MBIST -- _g11.5.2. _tMarch C- MBIST -- _g11.5.3. _tDisturb MBIST -- _g11.6. _tSummary -- _tReferences
650		0	_aDigital integrated circuits _xTesting
650		0	_aDigital integrated circuits _xDesign and construction
650		0	_aVerilog (Computer hardware description language)
655		4	_aElectronic books
773	0		_tSpringerLink _w(OCoLC)43927870
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-7548-5 _3SpringerLINK _zConnect to electronic resource
856	4	0	_uhttp://proxy.ohiolink.edu:9099/login?url=http://dx.doi.org/10.1007/978-1-4419-7548-5 _3SpringerLINK _zConnect to electronic resource (off-campus access)
942			_2ddc _cBK